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Low-Cost Memory Fault Tolerance for IoT Devices.

, , , , and . ACM Trans. Embed. Comput. Syst., 16 (5s): 128:1-128:25 (2017)

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Coding Assisted Adaptive Thresholding for Sneak-Path Mitigation in Resistive Memories., , and . ITW, page 1-5. IEEE, (2018)Parity++: Lightweight Error Correction for Last Level Caches., , , and . DSN Workshops, page 114-120. IEEE Computer Society, (2018)Order-optimal permutation codes in the generalized cayley metric., , and . ITW, page 234-238. IEEE, (2017)Software-Defined Error-Correcting Codes., , , and . DSN Workshops, page 276-282. IEEE Computer Society, (2016)Error Correction and Detection for Computing Memories Using System Side Information., , , , and . ITW, page 1-5. IEEE, (2018)Low-Cost Memory Fault Tolerance for IoT Devices., , , , and . ACM Trans. Embed. Comput. Syst., 16 (5s): 128:1-128:25 (2017)Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories., , , , , and . IEEE Trans. Inf. Theory, 65 (10): 6146-6159 (2019)Approximate file synchronization: Upper bounds and interactive algorithms., , , and . ITW, page 320-324. IEEE, (2016)Theoretical Bounds and Constructions of Codes in the Generalized Cayley Metric., , and . CoRR, (2018)A coding scheme for reliable in-memory hamming distance computation., , , and . ACSSC, page 1713-1717. IEEE, (2017)