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High speed Fp multipliers and adders on FPGA platform.

S. Ghosh, D. Mukhopadhyay, and D. Chowdhury. DASIP, page 21-26. IEEE, (2010)

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Santosh Kumar Ghosh

Santosh Panjikar

Santosh Noronha

Santosh Nepal

Santosh Vijayan

Other publications of authors with the same name

EM-X-DL: Efficient Cross-Device Deep Learning Side-Channel Attack with Noisy EM Signatures.J. Danial, D. Das, A. Golder, S. Ghosh, A. Raychowdhury, and S. Sen. CoRR, (2020)Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation.A. Ghosh, D. Das, J. Danial, V. De, S. Ghosh, and S. Sen. IEEE J. Solid State Circuits, 57 (1): 167-181 (2022)EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing.D. Das, J. Danial, A. Golder, N. Modak, S. Maity, B. Chatterjee, D. Seo, M. Chang, A. Varna, H. Krishnamurthy and 4 other author(s). IEEE J. Solid State Circuits, 56 (1): 136-150 (2021)Lightweight Design-for-Security Strategies for Combined Countermeasures Against Side Channel and Fault Analysis in IoT Applications.S. Patranabis, D. Roy, A. Chakraborty, N. Nagar, A. Singh, D. Mukhopadhyay, and S. Ghosh. J. Hardw. Syst. Secur., 3 (2): 103-131 (2019)Indian thermal power plant challenges and remedies via application of modified data envelopment analysis.V. Yadav, N. Kumar, S. Ghosh, and K. Singh. Int. Trans. Oper. Res., 21 (6): 955-977 (2014)High Speed Cryptoprocessor for η T Pairing on 128-bit Secure Supersingular Elliptic Curves over Characteristic Two Fields.S. Ghosh, D. Chowdhury, and A. Das. CHES, volume 6917 of Lecture Notes in Computer Science, page 442-458. Springer, (2011)Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks.A. Mondal, S. Ghosh, A. Das, and D. Chowdhury. VDAT, volume 7373 of Lecture Notes in Computer Science, page 370-372. Springer, (2012)Κ-Cipher: A Low Latency, Bit Length Parameterizable Cipher.M. Kounavis, S. Deutsch, S. Ghosh, and D. Durham. IACR Cryptology ePrint Archive, (2020)Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform.S. Ghosh, D. Mukhopadhyay, and D. Chowdhury. IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 434-442 (2013)Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator.M. Kar, A. Singh, S. Mathew, S. Ghosh, A. Rajan, V. De, R. Beyah, and S. Mukhopadhyay. CoRR, (2018)

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Disambiguation of "Ghosh, Santosh"

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High speed Fp multipliers and adders on FPGA platform.

Please choose a person to relate this publication to

Santosh Kumar Ghosh

Santosh Panjikar

Santosh Noronha

Santosh Nepal

Santosh Vijayan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ghosh, Santosh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML High speed Fp multipliers and adders on FPGA platform.

Please choose a person to relate this publication to

Santosh Kumar Ghosh

Santosh Panjikar

Santosh Noronha

Santosh Nepal

Santosh Vijayan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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High speed Fp multipliers and adders on FPGA platform.