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An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture.

, , , and . VLSID, page 133-138. IEEE, (2023)

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Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture., , and . Microelectron. J., (2022)An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture., , , and . VLSID, page 133-138. IEEE, (2023)An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices., , and . Circuits Syst. Signal Process., 42 (6): 3589-3616 (June 2023)Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation., and . VDAT, page 1-4. IEEE, (2020)Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard., , , and . VDAT, volume 1066 of Communications in Computer and Information Science, page 398-412. Springer, (2019)Parametric Performance Analysis of Synchronous and Asynchronous Heterogeneous Network on Chip., , and . iNIS, page 108-112. IEEE, (2016)Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems., , and . IEEE Consumer Electronics Magazine, 8 (3): 50-54 (2019)Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation., and . Microelectron. J., (2023)