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Другие публикации лиц с тем же именем

ROM based logic (RBL) design: High-performance and low-power adders., , и . ISCAS, стр. 796-799. IEEE, (2008)An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2765-2774 (2006)A process-tolerant cache architecture for improved yield in nanoscale technologies., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 13 (1): 27-38 (2005)Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (4): 743-751 (2007)Dynamic Noise Analysis with Capacitive and Inductive Coupling., , и . ASP-DAC/VLSI Design, стр. 65-70. IEEE Computer Society, (2002)Low-power design techniques for scaled technologies., , и . Integr., 39 (2): 64-89 (2006)Design Verification and Robust Design Technique for Cross-Talk Faults., , , и . Asian Test Symposium, стр. 449-. IEEE Computer Society, (2001)A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies., , и . IOLTS, стр. 149-154. IEEE Computer Society, (2004)Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits., , и . ITC, стр. 1269-1275. IEEE Computer Society, (2004)Novel sizing algorithm for yield improvement under process variation in nanometer technology., , и . DAC, стр. 454-459. ACM, (2004)