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A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS., and . IEEE J. Solid State Circuits, 35 (7): 1019-1024 (2000)Design of Components and Circuits Underneath Integrated Inductors., and . IEEE J. Solid State Circuits, 41 (10): 2265-2271 (2006)Analysis of Injection-Locked Ring Oscillators for Quadrature Clock Generation in Wireline or Optical Transceivers., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (8): 3074-3082 (2022)An Ultra-Wideband Impulse-Radio Transceiver Chipset Using Synchronized-OOK Modulation., , , and . IEEE J. Solid State Circuits, 46 (10): 2284-2299 (2011)Clockless, Continuous-Time Analog Correlator Using Time-Encoded Signal Processing Demonstrating Asynchronous CDMA for Wake-Up Receivers., and . IEEE J. Solid State Circuits, 55 (8): 2069-2081 (2020)Author's Response., , and . IEEE J. Solid State Circuits, 42 (10): 2315 (2007)Correction to Ä 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC"., , and . IEEE J. Solid State Circuits, 42 (10): 2315 (2007)Analysis and Design of a 0.6- to 10.5-GHz LNTA for Wideband Receivers., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (5): 431-435 (2015)Register file circuits and post-deployment framework to monitor aging effects in field., , and . ESSCIRC, page 425-428. IEEE, (2016)A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (1): 90-99 (2015)