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Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.

, , , , , and . SBCCI, page 95-100. IEEE Computer Society, (2002)

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Cell placement on graphics processing units., , , and . SBCCI, page 87-92. ACM, (2007)A study on the performance of fast initial placement algorithms., , and . VLSI-SOC, page 204-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing., , , and . SBCCI, page 220-225. ACM, (2006)Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias., , and . RITA, 19 (1): 28-45 (2012)Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1073-1086 (2009)An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias., , , and . VLSI-SoC, page 128-133. IEEE, (2006)Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits., , , and . ICECS, page 399-402. IEEE, (2006)Blue Macaw: A Didactic Placement Tool Using Simulated Annealing., , and . EDUTECH, volume 192 of IFIP, page 37-47. Springer, (2005)Improving run times by pruned application of synthesis transforms., , and . SBCCI, page 38-43. ACM, (2005)Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations., and . SBCCI, page 267-. IEEE Computer Society, (2003)