( en | de | ru )

 

Disambiguation of "Panda, Preeti Ranjan"

Author of the publication

copydeleteadd this publication to your clipboard
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (3): 339-352 (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Preeti Bajaj

Satyananda Panda

Preeti Kumari

Preeti Sareen

Preeti Bhargava

 

Other publications of authors with the same name

Managing Trace Summaries to Minimize Stalls During Postsilicon Validation., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (6): 1881-1894 (2017)Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems.. Int. J. Parallel Program., 36 (1): 1-2 (2008)A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009., and . J. Low Power Electron., 5 (3): 255-256 (2009)Data Memory Organization and Optimizations in Application-Specific Systems., , , , , , , and . IEEE Des. Test Comput., 18 (3): 56-68 (2001)On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems., , and . ACM Trans. Design Autom. Electr. Syst., 5 (3): 682-704 (2000)Low-power memory mapping through reducing address bus activity., and . IEEE Trans. Very Large Scale Integr. Syst., 7 (3): 309-320 (1999)PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor., and . ACM Trans. Embed. Comput. Syst., 18 (5s): 64:1-64:22 (2019)Techniques for Debug of Low Power SoCs., , , , , , , , , and . MTV, page 45-49. IEEE, (2019)Compressing Cache State for Postsilicon Processor Debug., , and . IEEE Trans. Computers, 60 (4): 484-497 (2011)FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation., , , and . CODES+ISSS, page 247-256. ACM, (2010)