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Disambiguation of "Mallick, Partha Sharathi"

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High-speed sub-threshold operation of carbon nanotube interconnects.

, , and . IET Circuits Devices Syst., 13 (4): 526-533 (2019)

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Partha Sampathkumaran

Ronzon Mallick

Rani Mallick

Bert Mallick

Bishawjit Mallick

 

Other publications of authors with the same name

Performance Analysis of Handover Schemes in Heterogeneous Networks., , , , and . Journal of Circuits, Systems, and Computers, 27 (11): 1850177:1-1850177:20 (2018)Low Complexity Compressive Sensing Greedy Detection of Generalized Quadrature Spatial Modulation., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (3): 632-635 (2018)Review on IMS-4G-cloud networks maintaining service continuity using distributed multi agent scheme., , and . Int. J. Comput. Aided Eng. Technol., 10 (5): 557-567 (2018)Design of 5-3 multicolumn compressor for high performance multiplier., , and . Int. J. Comput. Aided Eng. Technol., 10 (5): 568-575 (2018)Enhancement of test data compression with multistage encoding., , , , and . Integr., 47 (4): 499-509 (2014)Low-power selective pattern compression for scan-based test applications., , and . Comput. Electr. Eng., 40 (4): 1053-1063 (2014)FPGA design and implementation of truncated multipliers using bypassing technique., , , and . ICACCI, page 1111-1117. ACM, (2012)CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications., , , , and . ISED, page 135-139. IEEE, (2012)Design and Analysis of Multiplier Using Approximate 15-4 Compressor., , and . IEEE Access, (2017)Geometry-Based Crosstalk Reduction in CNT Interconnects., , and . J. Circuits Syst. Comput., 29 (6): 2050094:1-2050094:14 (2020)