( en | de | ru )

 

Disambiguation of "Liu, Shen-Iuan"

Author of the publication

copydeleteadd this publication to your clipboard
A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration.

, , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (3): 873-877 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kai-shen Liu

Liu Liu

Liu Liu

Liu Liu

Wan Shen

 

Other publications of authors with the same name

A 43.7mW 96GHz PLL in 65nm CMOS., and . ISSCC, page 276-277. IEEE, (2009)A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS., and . ISSCC, page 54-586. IEEE, (2007)CMOS oversampling Sigma-Delta magnetic to digital converters., , , and . ISCAS (1), page 388-391. IEEE, (2001)A low-input-swing AC-DC voltage multiplier using Schottky diodes., and . A-SSCC, page 245-248. IEEE, (2014)A 0.43pJ/bit true random number generator., , and . A-SSCC, page 33-36. IEEE, (2014)CMOS current-mode divider and its applications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 52-II (3): 145-148 (2005)A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider., , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (7): 555-559 (2009)A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector., and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 177-181 (2019)A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (11): 1094-1098 (2008)A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection., and . IEEE J. Solid State Circuits, 48 (2): 391-404 (2013)