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Другие публикации лиц с тем же именем

Isomorph-Redundancy in Sequential Circuits., , и . IEEE Trans. Computers, 49 (9): 992-997 (2000)Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability., , и . J. Electron. Test., 22 (2): 125-142 (2006)Fault diagnosis in reversible circuits under missing-gate fault model., , , и . Comput. Electr. Eng., 37 (4): 475-485 (2011)An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata., и . Microprocess. Microsystems, (2017)BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count., , и . J. Comput. Sci. Technol., 17 (6): 731-737 (2002)Cellular Automata Based Test Structures with Logic Folding., , , , и . VLSI Design, стр. 71-74. IEEE Computer Society, (2005)A New Synthesis of Symmetric Functions., , и . ASP-DAC/VLSI Design, стр. 160-165. IEEE Computer Society, (2002)Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking., , , , и . VLSID, стр. 246-251. IEEE, (2022)Partitioning-based test time reduction for core-based 3DICs., , и . VDAT, стр. 1-5. IEEE Computer Society, (2015)Testable design of AND-EXOR logic networks with universal test sets., , и . Comput. Electr. Eng., 35 (5): 644-658 (2009)