Author of the publication

s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.

Y. Choi, S. Hwang, Y. Lee, H. Park, J. Choi, J. Sim, and C. Kim. IEEE Access, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Andreas Choi

Youngmi Choi

Jinchul Choi

Chiwon Choi

Bongkyung Choi

Other publications of authors with the same name

A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE.J. Choi, Y. Choi, H. Park, J. Sim, Y. Kwon, S. Park, S. Kim, and C. Kim. IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 904-908 (March 2023)A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End.J. Sim, Y. Lee, H. Park, Y. Choi, J. Choi, and C. Kim. IEEE Trans. Circuits Syst. II Express Briefs, 69 (2): 404-408 (2022)A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications.S. Park, Y. Choi, J. Sim, J. Choi, H. Park, Y. Kwon, and C. Kim. ISSCC, page 118-119. IEEE, (2023)A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.H. Park, J. Sim, Y. Choi, J. Choi, Y. Kwon, S. Park, G. Park, J. Chung, K. Kim, H. Jung and 3 other author(s). IEEE J. Solid State Circuits, 56 (6): 1886-1896 (2021)A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.Y. Choi, S. Hwang, Y. Lee, H. Park, J. Choi, J. Sim, and C. Kim. IEEE Access, (2021)Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme.J. Choi, Y. Choi, H. Park, J. Sim, Y. Kwon, S. Park, and C. Kim. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (8): 3416-3427 (2022)29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.Y. Lee, Y. Choi, S. Bae, J. Jun, J. Song, S. Hwang, and C. Kim. ISSCC, page 490-491. IEEE, (2017)A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces.J. Choi, Y. Choi, J. Sim, Y. Kwon, S. Park, S. Kim, C. Sim, and C. Kim. IEEE J. Solid State Circuits, 59 (4): 1261-1270 (April 2024)30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links.H. Park, J. Song, J. Sim, Y. Choi, J. Choi, J. Yoo, and C. Kim. IEEE J. Solid State Circuits, 56 (2): 581-590 (2021)12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface.Y. Lee, Y. Choi, and C. Kim. ASP-DAC, page 287-288. IEEE, (2018)

BibSonomy

Disambiguation of "Choi, Yoonjae"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.

Please choose a person to relate this publication to

Andreas Choi

Youngmi Choi

Jinchul Choi

Chiwon Choi

Bongkyung Choi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Choi, Yoonjae"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.

Please choose a person to relate this publication to

Andreas Choi

Youngmi Choi

Jinchul Choi

Chiwon Choi

Bongkyung Choi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.