Author of the publication

Leveraging Energy Cycle Regularity to Predict Adaptive Mode for Non-volatile Processors.

, , , and . ASAP, page 189-196. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Data re-allocation enabled cache locking for embedded systems., , , , , and . J. Syst. Archit., (2017)Live Demonstration: A self-powered ultraviolet radiation monitoring platform based on nonvolatile processor., , , , and . ISCAS, page 1-. IEEE, (2018)Low power driven loop tiling for RRAM crossbar-based CNN., , , , and . SAC, page 375-380. ACM, (2018)A Novel Time Synchronization Method for Dynamic Reconfigurable Bus., , , , and . VLSI Design, (2016)On the Implication of NTC versus Dark Silicon on Emerging Scale-Out Workloads: The Multi-Core Architecture Perspective., , , , , and . IEEE Trans. Parallel Distributed Syst., 28 (8): 2314-2327 (2017)Expected Completion Time Aware Message Scheduling for UM-BUS Interconnected System., , , , , and . ISORC, page 60-66. IEEE Computer Society, (2017)A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion., , , , , , , and . NVMSA, page 7-12. IEEE, (2018)Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM., , and . DAC, page 106:1-106:6. ACM, (2014)BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors., , , , and . Microelectron. J., (2019)Efficient energy management by exploiting retention state for self-powered nonvolatile processors., , , , , , and . J. Syst. Archit., (2018)