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Sub-threshold Circuit Design with Shrinking CMOS Devices., , , and . ISCAS, page 2541-2544. IEEE, (2009)An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at VDD = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications., , , , , and . IEEE J. Solid State Circuits, 49 (1): 95-106 (2014)Serial sub-threshold circuits for ultra-low-power systems., and . ISLPED, page 27-32. ACM, (2009)A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83-92% efficiency across wide input and output voltages., , , , and . VLSIC, page 1-2. IEEE, (2014)An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions., , , , , and . ISSCC, page 432-433. IEEE, (2013)A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU., , , and . ISQED, page 98-102. IEEE, (2015)Flexible Circuits and Architectures for Ultralow Power., , , , and . Proc. IEEE, 98 (2): 267-282 (2010)Non-volatile logic SoC with software-hardware co-design and integrated supply supervisor for energy harvesting applications., , and . MWSCAS, page 887-889. IEEE, (2017)System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms., , , , and . ISCAS, page 269-272. IEEE, (2010)Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors., , , , , and . ISCAS, page 1437-1440. IEEE, (2009)