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A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO.

C. Pan, C. Shi, G. Zhao, B. Liu, L. Huang, and R. Zhang. IEICE Electron. Express, 19 (24): 20220432 (2022)

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Runxi He

Zhang Zhang

Meng Zhang

Methods and implementations of road-network matchingM. Zhang. TU München, (2009)

Xianghui Zhang

Yue Zhang

Other publications of authors with the same name

A 400-MS/s 10-Bit SAR-Assisted Two-Step Digital-Slope ADC.H. Deng, R. Zhang, and J. Chen. MWSCAS, page 987-990. IEEE, (2023)A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications.R. Zhang, H. Yang, Z. Zhang, C. Shi, Q. Fan, and J. Chen. ISCAS, page 1-4. IEEE, (2020)A 22-33 GHz Wideband CMOS LNA Using Low-k Non-inverting MCCRs for 5G mmW Communication Applications.Y. Zhang, Y. Xiang, X. Zhang, C. Shi, R. Zhang, and J. Chen. ASICON, page 1-4. IEEE, (2021)23.1 A 44μW IoT Tag Enabling 1μs Synchronization Accuracy and OFDMA Concurrent Communication with Software-Defined Modulation.J. Shen, F. Zhu, Y. Liu, B. Liu, C. Shi, L. Huang, L. Xu, X. Tian, and R. Zhang. ISSCC, page 400-402. IEEE, (2024)A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI.Y. Feng, H. Deng, Q. Fan, R. Zhang, P. Bikkina, and J. Chen. ISCAS, page 1-4. IEEE, (2020)A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO.C. Pan, C. Shi, G. Zhao, B. Liu, L. Huang, and R. Zhang. IEICE Electron. Express, 19 (24): 20220432 (2022)Machine-Learning Based Nonlinerity Correction for Coarse-Fine SAR-TDC Hybrid ADC.H. Deng, Q. Fan, R. Zhang, and J. Chen. MWSCAS, page 265-268. IEEE, (2020)A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC.H. Deng, P. Bikkina, E. Mikkola, R. Zhang, and J. Chen. ESSCIRC, page 337-340. IEEE, (2023)A 76-81 GHz CMOS mmW quadrature down-conversion mixer for automotive radar applications.S. Rao, C. Shi, and R. Zhang. IEICE Electron. Express, 17 (4): 20190740 (2020)A 64-84 GHz CMOS LNA with Excellent Gain Flatness for Wideband mmW Applications.X. Zhang, C. Shi, R. Zhang, H. Deng, and J. Chen. ISCAS, page 1-5. IEEE, (2021)

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Disambiguation of "Zhang, Runxi"

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A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO.

Please choose a person to relate this publication to

Runxi He

Zhang Zhang

Meng Zhang

Xianghui Zhang

Yue Zhang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zhang, Runxi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO.

Please choose a person to relate this publication to

Runxi He

Zhang Zhang

Meng Zhang

Xianghui Zhang

Yue Zhang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO.