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High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only).

, , , and . FPGA, page 278. ACM, (2011)

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Streaming Systems in FPGAs., and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 147-156. Springer, (2008)Using C-to-gates to program streaming image processing kernels efficiently on FPGAs., , and . FPL, page 626-630. IEEE, (2009)FINN: A Framework for Fast, Scalable Binarized Neural Network Inference., , , , , , and . CoRR, (2016)A Hash Table for Line-Rate Data Processing., , , and . ACM Trans. Reconfigurable Technol. Syst., 8 (2): 13:1-13:15 (2015)EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators., , , , , , , and . CoRR, (2022)Benchmarking vision kernels and neural network inference accelerators on embedded platforms., , , , , , , , and . J. Syst. Archit., (2021)Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs., , , , and . FPT, page 1-9. IEEE, (2019)The Future of Flexible HW Platform Architectures Panel Discussion., , , , , and . DATE, page 634. IEEE Computer Society / ACM, (2000)FAT: Training Neural Networks for Reliable Inference Under Hardware Faults., , , , and . ITC, page 1-10. IEEE, (2020)Trade-offs in the design of mixed hardware-software systems-a perspective from industry.. CODES, IEEE Computer Society, (1997)