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A tracking clock recovery receiver for 4-Gbps signaling., , and . IEEE Micro, 18 (1): 25-27 (1998)The GPU Computing Era., and . IEEE Micro, 30 (2): 56-69 (2010)Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks.. IEEE Trans. Computers, 40 (9): 1016-1023 (1991)Deadlock-Free Message Routing in Multiprocessor Interconnection Networks., and . IEEE Trans. Computers, 36 (5): 547-553 (1987)Comparing Reyes and OpenGL on a Stream Architecture., , , and . Graphics Hardware, page 47-56. The Eurographics Association, (2002)A Universal Parallel Computer Architecture.. FGCS, page 746-758. IOS Press, (1992)Issues in the Design and Implementation of Instruction Processors for Multicomputers (Position Statement).. Multithreaded Computer Architecture, volume 281 of The Kluwer International Series in Engineering and Computer Science, Kluwer / Springer, (1994)SpArch: Efficient Architecture for Sparse Matrix Multiplication., , , and . HPCA, page 261-274. IEEE, (2020)DSD: Dense-Sparse-Dense Training for Deep Neural Networks., , , , , , , , , and 2 other author(s). ICLR (Poster), OpenReview.net, (2017)Efficient Sparse-Winograd Convolutional Neural Networks., , , and . ICLR (Poster), OpenReview.net, (2018)