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Benchmarking TFET from a circuit level perspective: Applications and guideline., , , , , , , and . ISCAS, page 1-4. IEEE, (2017)New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology., , , , , , , , , and 3 other author(s). IRPS, page 3-1. IEEE, (2018)A 3D multi-layer CMOS-RRAM accelerator for neural network., , , , , , and . 3DIC, page 1-5. IEEE, (2016)OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits., , , , , , and . ASICON, page 1-4. IEEE, (2019)Realization of Nanoscale Neuromorphic Memristor Array with Low Power Consumption., , , , , , , and . ASICON, page 1-4. IEEE, (2019)Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life., , and . ICICDT, page 1-3. IEEE, (2016)Neuromorphic Devices and Networks Based on Memristors with Ionic Dynamics., , and . Handbook of Memristor Networks, Springer, (2019)New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework., , , , , , , , and . CoRR, (2019)Recursive integral method with Cayley transformation., , and . Numerical Lin. Alg. with Applic., (2018)Evaluation of SRAM Vmin shift induced by random telegraph noise (RTN): physical understanding and prediction method., , , , , and . ISCAS, page 1-4. IEEE, (2018)