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An address gneration unit for array accessing., and . SIGARCH Comput. Archit. News, 17 (6): 154-160 (1989)The K1-Map Reduction for Pattern Classifications., and . IEEE Trans. Pattern Anal. Mach. Intell., 19 (6): 616-622 (1997)A hardware mechanism for priority queue., and . SIGARCH Comput. Archit. News, 17 (6): 162-169 (1989)A comment on ä fetch - and - op implementation for parallel computers"., and . SIGARCH Comput. Archit. News, 18 (1): 32 (1990)Perceptron-perceptron net., and . Pattern Recognit. Lett., 19 (7): 559-568 (1998)A simple architecture for constant time sorting machines., and . SIGARCH Comput. Archit. News, 23 (1): 13-19 (1995)Comments on Ön the design of feedforward neural networks for binary mapping 1"., and . Neurocomputing, 9 (1): 81-84 (1995)Logic and conflict-free vector addresses., and . SIGARCH Comput. Archit. News, 17 (6): 150-153 (1989)k-winners-take-all neural net with Θ(1) time complexity., and . IEEE Trans. Neural Networks, 8 (6): 1557-1561 (1997)