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Другие публикации лиц с тем же именем

On using a SPICE-like TSTAC™ eFlash model for design and test., , , , , , , , и . DDECS, стр. 359-364. IEEE Computer Society, (2011)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , и . European Test Symposium, стр. 81-86. IEEE Computer Society, (2010)Evaluation of design for reliability techniques in embedded flash memories., , , и . DATE, стр. 1593-1598. EDA Consortium, San Jose, CA, USA, (2007)Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories., , , и . ETS, стр. 84-90. IEEE Computer Society, (2008)Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories., , , , , , , , и . J. Electron. Test., 28 (2): 215-228 (2012)NAND flash testing: A preliminary study on actual defects., , , , , , и . ITC, стр. 1. IEEE Computer Society, (2009)Architecture for Highly Reliable Embedded Flash Memories., , , и . DDECS, стр. 75-80. IEEE Computer Society, (2007)