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Disambiguation of "Beuchat, Jean-Luc"

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Hardware Reconfigurable Neural Networks.

, , and . IPPS/SPDP Workshops, volume 1388 of Lecture Notes in Computer Science, page 91-98. Springer, (1998)

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Jean-Luc Rebière

Jean-Luc Wolfender

Jean-Luc Boevé

Jean-Luc Régnier

Jean-Luc Wagner

 

Other publications of authors with the same name

Guest Editorial: Introduction to the Special Section on Emerging Security Trends for Biomedical Computations, Devices, and Infrastructures., , , and . IEEE ACM Trans. Comput. Biol. Bioinform., 13 (3): 399-400 (2016)A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO., , and . J. Cryptogr. Eng., 1 (2): 101-121 (2011)A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function Grøstl., , , , and . IACR Cryptology ePrint Archive, (2012)An On-Line Arithmetic-Based Reconfigurable Neuroprocessor., and . IPPS/SPDP Workshops, volume 1586 of Lecture Notes in Computer Science, page 700-702. Springer, (1999)FPGA and ASIC implementations of the etaT pairing in characteristic three., , , , , , , , , and 6 other author(s). Comput. Electr. Eng., 36 (1): 73-87 (2010)Arithmetic Operators for Pairing-Based Cryptography., , , and . CHES, volume 4727 of Lecture Notes in Computer Science, page 239-255. Springer, (2007)High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves., , , , , and . Pairing, volume 6487 of Lecture Notes in Computer Science, page 21-39. Springer, (2010)Compact Implementation of Threefish and Skein on FPGA., , and . NTMS, page 1-5. IEEE, (2012)Some Modular Adders and Multipliers for Field Programmable Gate Arrays.. IPDPS, page 190. IEEE Computer Society, (2003)Hardware Reconfigurable Neural Networks., , and . IPPS/SPDP Workshops, volume 1388 of Lecture Notes in Computer Science, page 91-98. Springer, (1998)