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Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm.

, , and . Int. J. Reconfigurable Comput., (2013)

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Design and optimization of multithreshold CMOS (MTCMOS) circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (10): 1324-1342 (2003)A scalable pipelined architecture for real-time computation of MLP-BP neural networks., , and . Microprocess. Microsystems, 36 (2): 138-150 (2012)StarPlace: A new analytic method for FPGA placement., , and . Integr., 44 (3): 192-204 (2011)Multisource Domain Adaptation for Remote Sensing Using Deep Neural Networks., , and . IEEE Trans. Geosci. Remote. Sens., 58 (5): 3328-3340 (2020)Corrigendum to "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm"., , and . Int. J. Reconfigurable Comput., (2018)A Genetic Algorithm Hardware Accelerator for VLSI Circuit Partitioning., , and . Int. J. Comput. Their Appl., 12 (3): 163-180 (2005)Using Machine Learning to Predict Operating Frequency During Placement in FPGA Designs., , , and . ICM, page 53-56. IEEE, (2021)An Adaptive Sequential Decision Making Flow for FPGAs using Machine Learning., , , and . ICM, page 34-37. IEEE, (2022)Comparing Classifiers in Historical Census Linkage., , , , , and . ICDM Workshops, page 1086-1094. IEEE Computer Society, (2014)A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays., , and . ReConFig, IEEE Computer Society, (2005)