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Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays., , , and . FPT, page 33-40. IEEE, (2004)Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects., , , , , and . J. Supercomput., 21 (2): 131-144 (2002)Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications., , , , , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 1135-1138. Springer, (2002)A SW/HW Interface API for Java/FPGA Co-Designed Applets., , , , , and . FCCM, page 269-270. IEEE Computer Society, (2001)A new algorithm for elimination of common subexpressions., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (1): 58-68 (1999)Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java., , , , , , and . SCOPES, volume 2826 of Lecture Notes in Computer Science, page 313-328. Springer, (2003)Highly scalable network on chip for reconfigurable systems., , , , , , and . SoC, page 79-82. IEEE, (2003)Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip., , , , , and . DATE, page 10986-10993. IEEE Computer Society, (2003)Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms., , , , and . FCCM, page 278-279. IEEE Computer Society, (2003)Functional verification of an embedded network component by co-simulation with a real network., , , and . HLDVT, page 64-67. IEEE Computer Society, (2000)