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Disambiguation of "Xiu, Liming"

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A Method of Low-Cost Pure-Digital GPS Disciplined Clock for Improving Frequency Accuracy and Steering Frequency Through TAF-DPS Frequency Synthesizer.

, , , , , and . IEEE Trans. Instrum. Meas., (2021)

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Liming Zhu

Liming Lu

Xingqiang Xiu

Fengli Xiu

Liming Gao

 

Other publications of authors with the same name

Direct Period Synthesis for Achieving Sub-PPM Frequency Resolution Through Time Average Frequency: The Principle, The Experimental Demonstration, and Its Application in Digital Communication.. IEEE Trans. Very Large Scale Integr. Syst., 23 (7): 1335-1344 (2015)A "Flying-Adder" frequency synthesis architecture of reducing VCO stages., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (2): 201-210 (2005)Analysis of Harmonic Energy Distribution Portfolio for Digital-to-Frequency Converters., , and . IEEE Trans. Instrumentation and Measurement, 59 (10): 2770-2778 (2010)A Method of Low-Cost Pure-Digital GPS Disciplined Clock for Improving Frequency Accuracy and Steering Frequency Through TAF-DPS Frequency Synthesizer., , , , , and . IEEE Trans. Instrum. Meas., (2021)Crack Fault Diagnosis Based on MEP Based Neural Network., , , and . ISCSCT (1), page 635-639. IEEE Computer Society, (2008)A 0.02 Ppb/Step Wide Range DCXO Based on Time-Average-Frequency: Demonstration on FPGA., and . ISCAS, page 1-5. IEEE, (2019)A comparative study between Fractional-N PLL and Flying-Adder PLL., , and . ISCAS, page 237-240. IEEE, (2010)All digital FPGA-implementable time-average-frequency direct period synthesis for IoT applications.. ISCAS, page 1-4. IEEE, (2017)Using All-Digital On-Chip Syntonistor to Compensate Clock Frequency Error in Network Time Synchronization for Accuracy Reaching to Sub-µs Range., , , , , and . IEEE Trans. Ind. Electron., 70 (10): 9981-9991 (October 2023)A novel all-digital PLL with software adaptive filter., , , and . IEEE J. Solid State Circuits, 39 (3): 476-483 (2004)