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PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine.

, , , and . Integr., (2017)

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Synthesizable delay line architectures for digitally controlled voltage regulators., , , and . SoCC, page 72-77. IEEE, (2012)Multi-bit error control coding with limited correction for high-performance and energy-efficient network on chip., , , , and . IET Circuits Devices Syst., 14 (1): 7-16 (2020)Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5681-5694 (2022)A 93% Peak Efficiency Fully-Integrated Multilevel Multistate Hybrid DC-DC Converter., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (8): 2617-2630 (2018)A simple hybrid 3-level buck-boost DC-DC converter with efficient PWM regulation scheme., , , and . ICECS, page 368-371. IEEE, (2015)A 1 GS/s 6-bit time-based analog-to-digital converter (T-ADC) for front-end receivers., , , , , and . MWSCAS, page 1605-1608. IEEE, (2017)Area-efficient read/write circuit for spintronic memristor based memories., , , , , and . MWSCAS, page 1544-1547. IEEE, (2017)PASSIOT: A pareto-optimal multi-objective optimization approach for synthesis of analog circuits using sobol' indices-based engine., , , and . MWSCAS, page 1-4. IEEE, (2016)A 3D model of quadrupole dielectrophoresis levitation., , , , and . MWSCAS, page 1-4. IEEE, (2016)Performance evaluation of finFET based SRAM under statistical VT variability., , , and . ICM, page 88-91. IEEE, (2014)