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Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (7): 432-436 (2013)Analysis and Evaluations of Reliability of Reconfigurable FPGAs., , , , , and . J. Electron. Test., 24 (1-3): 105-116 (2008)Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders., , , , and . IEEE Trans. Computers, 55 (5): 534-540 (2006)Tile-based QCA design using majority-like logic primitives., , , , and . JETC, 1 (3): 163-185 (2005)Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering., , , , and . DTIS, page 1-2. IEEE, (2018)Two-Dimensional Schemes for Clocking/Timing of QCA Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 34-44 (2008)Soft Error Tolerant Count Min Sketches., , and . IEEE Trans. Computers, 70 (2): 284-290 (2021)Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability., , , and . IOLTS, page 1-5. IEEE, (2022)A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses., , , , and . DFT, page 1-6. IEEE, (2021)Fault Modeling and Simulation of Memristor based Gas Sensors., , , , , and . IOLTS, page 58-59. IEEE, (2019)