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Minimum Length Synchronizing Sequences of Finite State Machine.

, , and . DAC, page 463-468. ACM Press, (1993)

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Formal Verification of FIRE: A Case Study., , , and . DAC, page 173-177. ACM Press, (1997)The Verifiacation Problem for Safe Replaceability., and . CAV, volume 818 of Lecture Notes in Computer Science, page 311-323. Springer, (1994)Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders., and . FMCAD, volume 3312 of Lecture Notes in Computer Science, page 144-158. Springer, (2004)Panel Summaries., and . IEEE Des. Test Comput., 20 (4): 86-88 (2003)Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits.. IEEE Des. Test Comput., 18 (4): 4-5 (2001)Guest Editors' Introduction: The True State of the Art of ESL Design., , and . IEEE Des. Test Comput., 23 (5): 335-337 (2006)Integrated Formal and Informal Design Verification of Commercial Integrated Circuits., , and . PDPTA, page 1061-1068. CSREA Press, (1999)Constraint synthesis for environment modeling in functional verification., , , and . DAC, page 296-299. ACM, (2003)Synchronizing sequences and symbolic traversal techniques in test generation., , , and . J. Electron. Test., 4 (1): 19-31 (1993)Exact calculation of synchronizing sequences based on binary decision diagrams., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (8): 1024-1034 (1994)