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High Density Integrated Computing Circuitry with Multiple Valued Logic.. IEEE Trans. Computers, 29 (2): 191-195 (1980)Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders.. IEEE Trans. Computers, 29 (5): 400-403 (1980)A unified DCT/IDCT architecture for VLSI implementation., , , and . ICASSP, page 1993-1996. IEEE, (1988)Voltage Comparator Circuits for Multiple-Valued CMOS Logic., and . ISMVL, page 67-75. IEEE Computer Society, (2002)Low-Power Voltage Comparator Circuit for CMOS Quaternary Logic., and . J. Multiple Valued Log. Soft Comput., 10 (3): 225-260 (2004)A VLSI architecture for two-dimensional Radon transform computations., , , and . ICASSP, page 933-936. IEEE, (1990)Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs., , and . ISCAS, page 2090-2093. IEEE, (1993)An architecture for region boundary extraction in raster scan images suitable for VLSI implementation., , , and . Mach. Vis. Appl., 2 (4): 193-214 (1989)Clocked CMOS adiabatic logic with integrated single-phase power-clock supply., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (4): 460-463 (2000)A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 724-732. Springer, (2005)