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A novel damped-wave framework for macro placement., , и . ICCAD, стр. 504-511. IEEE, (2017)NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (12): 1914-1927 (2014)Effective Wire Models for X-Architecture Placement., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (4): 654-658 (2008)MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1621-1634 (2008)An integrated nonlinear placement framework with congestion and porosity aware buffer planning., , и . DAC, стр. 702-707. ACM, (2008)X-architecture placement based on effective wire models., , и . ISPD, стр. 87-94. ACM, (2007)MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs., , , и . ASP-DAC, стр. 557-562. ACM, (2019)SoC test scheduling using the B-tree based floorplanning technique., , и . ASP-DAC, стр. 1188-1191. ACM Press, (2005)MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs., , , , и . DAC, стр. 447-452. IEEE, (2007)Double patterning lithography-aware analog placement., , , , и . DAC, стр. 4:1-4:6. ACM, (2013)