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Disambiguation of "Lou, Pang-Yen"

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74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (10): 2464-2468 (2019)

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Min Lou

Vincent Pang

Yen Yen Kwan

Xinghua Lou

Yu Lou

 

Other publications of authors with the same name

High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors., , , , , , and . Circuits Syst. Signal Process., 40 (9): 4187-4195 (2021)A Broken Line Detection Circuit for Multi-cell Li-ion Battery Module1., , and . ICCE, page 1-2. IEEE, (2019)0.7 % error rate 3A bidirectional current sensor using high voltage CMOS process., , , and . Microelectron. J., (2021)74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (10): 2464-2468 (2019)A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process., , , , , , , and . Integr., (May 2023)State of charge, state of health, and state of function monitoring for EV BMS., , and . ICCE, page 310-311. IEEE, (2017)2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process., , , , and . Circuits Syst. Signal Process., 40 (6): 2824-2840 (2021)On-chip CMOS Corner Detector Design for Panel Drivers., , and . ISOCC, page 11-12. IEEE, (2021)Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer., , and . ISOCC, page 1-2. IEEE, (2021)