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Disambiguation of "Tadros, Ramy N."

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The 2010 Census Confidentiality Protections Failed, Here's How and Why.

, , , , , , , , , , , , , and . CoRR, (2023)

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Nabil Tadros

Ramy Zoubi

Yehia Tadros

Ramy Ammar

 

Other publications of authors with the same name

A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures., and . ACM Trans. Design Autom. Electr. Syst., 25 (2): 16:1-16:28 (2020)A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (9): 858-862 (2016)A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks., , , and . ISCAS, page 1520-1523. IEEE, (2014)The 2010 Census Confidentiality Protections Failed, Here's How and Why., , , , , , , , , and 4 other author(s). CoRR, (2023)Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications., , , , , and . ASYNC, page 11-18. IEEE Computer Society, (2016)A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme., , , and . ICEAC, page 1-4. IEEE, (2015)A Robust and Self-Adaptive Clocking Technique for RSFQ Circuits - The Architecture., and . ISCAS, page 1-5. IEEE, (2018)A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits., , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (2): 15:1-15:23 (2016)Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks., , , and . ISCAS, page 2752-2755. IEEE, (2014)Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures., , and . ISLPED, page 16-21. ACM, (2016)