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16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.

, , , , , , , , , , , , , , and . ISSCC, page 260-262. IEEE, (2020)

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16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter., , , , , , , , , and 5 other author(s). ISSCC, page 260-262. IEEE, (2020)A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB., and . VLSIC, page 166-167. IEEE, (2012)A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB., and . IEEE J. Solid State Circuits, 48 (4): 983-995 (2013)A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC., and . IEEE J. Solid State Circuits, 45 (12): 2634-2646 (2010)A mostly digital variable-rate continuous-time ADC ΔΣ modulator., and . ISSCC, page 298-299. IEEE, (2010)Improved neurodevelopmental outcomes for extremely low birth weight infants in 2000-2002., , , , , , and . Pediatrics, 119 (1): 37--45 (January 2007)A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither., , , , , , , , , and 7 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Correction to Ä Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" Nov 10 2250-2261., and . IEEE J. Solid State Circuits, 46 (5): 1231 (2011)22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors., , , , , , , , , and 3 other author(s). ISSCC, page 390-392. IEEE, (2024)Grades I-II intraventricular hemorrhage in extremely low birth weight infants: effects on neurodevelopment., , , , and . J Pediatr, 149 (2): 169--173 (August 2006)