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LDP: Learnable Dynamic Precision for Efficient Deep Neural Network Training and Inference.

, , , , , and . CoRR, (2022)

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An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era., , , , , and . HPCC/CSS/ICESS, page 688-693. IEEE, (2015)Predicting for I/O stack optimizations on cyber-physical systems., , , and . Microprocess. Microsystems, (2023)Automated Optical Accelerator Search: Expediting Green and Ubiquitous DNN-Powered Intelligence., , , , , and . IEEE Des. Test, 40 (6): 175-184 (December 2023)Contention Minimized Bypassing in SMART NoC., , , , and . ASP-DAC, page 205-210. IEEE, (2020)Fixed priority scheduling of real-time flows with arbitrary deadlines on smart NoCs: work-in-progress., , , , and . EMSOFT Companion, page 6:1-6:2. ACM, (2017)Chip Temperature Optimization for Dark Silicon Many-Core Systems., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (5): 941-953 (2018)User Experience-Enhanced and Energy-Efficient Task Scheduling on Heterogeneous Multi-Core Mobile Systems., , , , , , and . ICPADS, page 283-290. IEEE, (2018)Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (1): 1-14 (2019)FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era., , , , , and . IEEE Trans. Parallel Distributed Syst., 28 (7): 1905-1918 (2017)Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (7): 1381-1394 (2021)