Author of the publication

A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder.

, and . IEEE Trans. Very Large Scale Integr. Syst., 17 (6): 838-843 (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding., and . ISCAS, page 256-259. IEEE, (2008)A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC., , and . ISCAS (5), page 4525-4528. IEEE, (2005)An AMBA-compliant deblocking filter IP for H.264/AVC., , and . ISCAS (5), page 4529-4532. IEEE, (2005)A Systolic Algorithm for the k-Nearest Neighbors Problem., , and . IEEE Trans. Computers, 41 (1): 103-108 (1992)Channel density reduction by routing over the cells., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (8): 1067-1071 (1991)A fast transistor-chaining algorithm for CMOS cell layout., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (7): 781-786 (1990)Effective enforcement of path-delay constraints inperformance-driven placement., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (1): 15-22 (2002)An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration., and . ACM Trans. Embed. Comput. Syst., 9 (4): 35:1-35:39 (2010)Integration, Verification and Layout of a Complex Multimedia SOC, , and . CoRR, (2007)Optimum and Heuristic Data Path Scheduling Under Resource Constraints., , and . DAC, page 65-70. IEEE Computer Society Press, (1990)