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Disambiguation of "Hashimoto, Masanori"

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When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies.

, , , , , and . CoRR, (2019)

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Setsuko Hashimoto

Marcelo Hashimoto

Jujiro Hashimoto

Yoko Hashimoto

 

Other publications of authors with the same name

Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (4): 724-731 (2007)A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (12): 1447-1455 (2020)Transistor Sizing of LCD Driver Circuit for Technology Migration., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2712-2717 (2007)Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2441-2446 (2010)A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2292-2300 (2012)Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices., , , , , and . IEICE Trans. Inf. Syst., 96-D (8): 1624-1631 (2013)Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (10): 3978-3991 (October 2023)Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate., and . IEICE Trans. Electron., 102-C (4): 296-302 (2019)Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (4): 541-553 (2009)A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design., , and . DAC, page 446-451. ACM Press, (1999)