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Disambiguation of "Legat, Jean-Didier"

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A fully-synthesized 20-gate digital spike-based synapse with embedded online learning.

, , , and . ISCAS, page 1-4. IEEE, (2017)

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Gerhard Legat

Georg Legath

Daniel Legat

Martin Legat

Miriam Legat

 

Other publications of authors with the same name

Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2561-2570 (2014)Interests and Limitations of Technology Scaling for Subthreshold Logic., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1508-1519 (2009)Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI., , , , and . Microelectron. J., (2016)An efficient metric of setup time for pulsed flip-flops based on output transition time., , , , and . ICICDT, page 9-12. IEEE, (2013)A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations., , , , and . J. Low Power Electron., 10 (1): 118-126 (2014)A fully-synthesized 20-gate digital spike-based synapse with embedded online learning., , , and . ISCAS, page 1-4. IEEE, (2017)SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes., , , , , , , and . IEEE J. Solid State Circuits, 48 (1): 20-32 (2013)MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning., , and . IEEE Trans. Biomed. Circuits Syst., 13 (5): 999-1010 (2019)A 0.086-mm2 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS., , and . CoRR, (2018)Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits., , and . ISLPED, page 21-26. ACM, (2009)