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Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits.

, , , , and . Annual Simulation Symposium, page 213-220. IEEE Computer Society, (2007)

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Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition., , , , and . DSD, page 132-137. IEEE Computer Society, (2007)A combined tree growing technique for block-test scheduling under power constraints., , and . ISCAS (5), page 255-258. IEEE, (2001)Parity-based Concurrent Error-detection Architecture Applied to the IDEA NXT Crypto-algorithm., , and . SOFA (1), volume 356 of Advances in Intelligent Systems and Computing, page 713-724. Springer, (2014)The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation., , and . Annual Simulation Symposium, page 217-224. IEEE Computer Society, (2005)Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits., , , , and . Annual Simulation Symposium, page 213-220. IEEE Computer Society, (2007)Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints., , , and . IEEE International Workshop on Rapid System Prototyping, page 162-167. IEEE Computer Society, (2001)Intrusions Detection in Intelligent Agent-Based Non-traditional Grids., and . ICETC, page 116-121. IEEE Computer Society, (2009)Computer Arithmetic - Algorithms and Hardware Implementations.. Springer, (2012)Multiple-level concatenated coding in embryonics: a dependability analysis., , and . GECCO, page 941-948. ACM, (2005)A high-speed AES architecture implementation., , , and . Conf. Computing Frontiers, page 95-96. ACM, (2010)