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Disambiguation of "Perrott, Michael H."

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A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 48 (1): 276-291 (2013)

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Michael H Stieglitz

Michael H Schoenberg

Michael H Holthausen

Michael H Thung

Michael H Bischof

 

Other publications of authors with the same name

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation., , and . IEEE J. Solid State Circuits, 32 (11): 2048-2060 (1997)A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise., and . IEEE J. Solid State Circuits, 41 (4): 966-980 (2006)Session 15 overview: Data converter techniques., and . ISSCC, page 266-267. IEEE, (2013)Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.. DAC, page 498-503. ACM, (2002)A clockless, multi-stable, CMOS analog circuit., and . ISCAS, page 1764-1767. IEEE, (2014)A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping., and . IEEE J. Solid State Circuits, 44 (4): 1089-1098 (2009)A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance., , , and . IEEE J. Solid State Circuits, 43 (4): 855-863 (2008)A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation., , and . IEEE J. Solid State Circuits, 43 (12): 2776-2786 (2008)A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer., and . IEEE J. Solid State Circuits, 43 (4): 805-814 (2008)A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer., , and . ISSCC, page 384-385. IEEE, (2013)