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Disambiguation of "Nepal, Kundan"

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Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.

, , , , , , and . J. Electron. Test., 35 (6): 887-900 (2019)

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Santosh Nepal

Santosh Nepal

Ranjita Nepal

 

Other publications of authors with the same name

Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications., , , and . CCWC, page 228-233. IEEE, (2020)Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (4): 502-515 (2005)MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits., , , , and . IEEE Micro, 26 (5): 19-27 (2006)Enhancing online error detection through area-efficient multi-site implications., , , , and . VTS, page 241-246. IEEE Computer Society, (2011)Improving the testability and reliability of sequential circuits with invariant logic., , , and . ACM Great Lakes Symposium on VLSI, page 131-134. ACM, (2010)Designing MRF based error correcting circuits for memory elements., , , , and . DATE, page 792-793. European Design and Automation Association, Leuven, Belgium, (2006)Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits., , , , and . DATE, page 576-581. EDA Consortium, San Jose, CA, USA, (2007)Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack., , , , , , and . J. Electron. Test., 35 (6): 887-900 (2019)Tools for the 3Cs of Entrepreneurially Minded Learning (EML)., , , and . FIE, page 1-3. IEEE, (2018)Low-cost instrumentation of high-tunnels for a small co-op farm., , , and . GHTC, page 1-4. IEEE, (2019)