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Power-constrained test scheduling for multi-clock domain SoCs.

, , and . DATE, page 297-302. European Design and Automation Association, Leuven, Belgium, (2006)

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Test Scheduling for Multi-Clock Domain SoCs under Power Constraint., , and . IEICE Trans. Inf. Syst., 91-D (3): 747-755 (2008)Power-constrained test scheduling for multi-clock domain SoCs., , and . DATE, page 297-302. European Design and Automation Association, Leuven, Belgium, (2006)