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Disambiguation of "Lu, Guangyi"

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Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process.

, , , and . ISCAS, page 1-4. IEEE, (2017)

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Lu Lu

Jing Lu

Qianhao Lu

Lu Zhang

Yanfeng Lu

 

Other publications of authors with the same name

Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process., , , and . ISCAS, page 1-4. IEEE, (2017)A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics., , and . IEEE Access, (2020)Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits., , , , , and . ASICON, page 1-4. IEEE, (2013)A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications., , , , and . ISCAS, page 265-268. IEEE, (2016)Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 4413-4422 (December 2023)Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling., , , , , and . Sci. China Inf. Sci., 58 (4): 1-9 (2015)Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process., , , , and . Sci. China Inf. Sci., 59 (12): 122401:1-122401:9 (2016)Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process., , , , , and . Sci. China Inf. Sci., 59 (4): 042407:1-042407:9 (2016)A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network., , , , and . ASICON, page 1-4. IEEE, (2015)A compact SCR model using advanced BJT models and standard SPICE elements., , , , and . Sci. China Inf. Sci., 59 (10): 109302 (2016)