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Disambiguation of "Amirkhany, Amir"

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An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.

, , , , , and . CICC, page 1-4. IEEE, (2011)

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Manutschehr Amirfeyz

Iradj Amirzadeh-Asl

Mahmud Amirian-Khaffadjeh

Belal Amireh

Mansoor Anwer Ismail Amir

 

Other publications of authors with the same name

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration., , , , , , , , , and 1 other author(s). ISSCC, page 132-134. IEEE, (2012)Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links., , , and . GLOBECOM, IEEE, (2006)A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS., , and . ISSCC, page 42-43. IEEE, (2013)A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (3): 636-648 (2013)A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link., , , , , , , , and . ISSCC, page 138-140. IEEE, (2012)Time-Variant Characterization and Compensation of Wideband Circuits., , , and . CICC, page 487-490. IEEE, (2007)A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link., , , , , , , , and . IEEE J. Solid State Circuits, 47 (12): 3208-3219 (2012)A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links., , and . IEEE J. Solid State Circuits, 45 (8): 1533-1541 (2010)Multi-tone signaling for high-speed backplane electrical links., , and . GLOBECOM, page 1111-1117. IEEE, (2004)Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee., , and . ISSCC, page 178-179. IEEE, (2021)