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Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.

, , , and . J. Low Power Electron., 6 (1): 192-200 (2010)

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Transistor sizing in lithography-aware regular fabrics., , , , and . SBCCI, page 97-102. ACM, (2011)Lithography analysis of via-configurable transistor-array fabrics., , and . NORCHIP, page 1-4. IEEE, (2012)Analytical logical effort formulation for minimum active area under delay constraints., , , and . SBCCI, page 1-6. IEEE, (2013)Transistor Sizing Analysis of Regular Fabrics., , , , and . ARCS Workshops, VDE-Verlag, (2011)Transistor network restructuring against NBTI degradation., , , and . Microelectron. Reliab., 50 (9-11): 1298-1303 (2010)Design of CMOS logic gates with enhanced robustness against aging degradation., , , and . Microelectron. Reliab., 52 (9-10): 1822-1826 (2012)SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC., , , and . IEEE Trans. Emerg. Top. Comput., 5 (2): 247-259 (2017)SAT based environment for logical capacity evaluation of via configurable block templates.. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil, (2016)ndltd.org (oai:agregador.ibict.br.BDTD_UFRGS:oai:www.lume.ufrgs.br:10183/142737).BTI and HCI first-order aging estimation for early use in standard cell technology mapping., , , and . Microelectron. Reliab., 53 (9-11): 1360-1364 (2013)Impact and optimization of lithography-aware regular layout in digital circuit design., , , , and . ICCD, page 279-284. IEEE Computer Society, (2011)