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Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems., , and . ICPP (1), page 326-330. Pennsylvania State University Press, (1990)P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP., , , and . ISQED, page 176-183. IEEE, (2010)Fault-Tolerant Multiprocessor Link and Bus Network Architectures.. IEEE Trans. Computers, 34 (1): 33-45 (1985)Correction: IEEE Transactions on Computers 35(1): 94 (1986).An application specific processor for implementing stack filters., , and . ASAP, page 196-199. IEEE, (1993)Program Fault Tolerance Based on Memory Access Behavior., and . FTCS, page 426-435. IEEE Computer Society, (1991)Guest Editorial: Special Issue on "Secure and Fault-Tolerant Embedded Computing"., , and . ACM Trans. Embed. Comput. Syst., 16 (4): 92:1-92:2 (2017)Consensus With Dual Failure Modes., and . IEEE Trans. Parallel Distributed Syst., 2 (2): 214-222 (1991)A novel framework for logic verification in a synthesis environment., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (1): 20-32 (1996)Job Scheduling in Mesh Multicomputers., and . IEEE Trans. Parallel Distributed Syst., 9 (1): 57-70 (1998)The Hyper-deBruijn Networks: Scalable Versatile Architecture., and . IEEE Trans. Parallel Distributed Syst., 4 (9): 962-978 (1993)