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Scaling CMOS beyond Si FinFET: an analog/RF perspective., , , , , , , , , и 4 other автор(ы). ESSDERC, стр. 158-161. IEEE, (2018)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies., , , , , , , , , и 6 other автор(ы). ESSDERC, стр. 102-105. IEEE, (2014)Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling., , , , , , , и . ICICDT, стр. 51-54. IEEE, (2022)Beyond-Si materials and devices for more Moore and more than Moore applications., , , , , , , , , и 16 other автор(ы). ICICDT, стр. 1-5. IEEE, (2016)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , и 2 other автор(ы). DAC, стр. 13. ACM, (2019)Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors., , , , , , , , , и 8 other автор(ы). Microelectron. Reliab., 47 (4-5): 521-524 (2007)Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices., , , , , и . Microelectron. J., (2021)Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors., , , , , , , и . ASICON, стр. 1-4. IEEE, (2019)NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase., , , , , , , и . Microelectron. Reliab., 47 (4-5): 505-507 (2007)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , и 34 other автор(ы). VLSI Technology and Circuits, стр. 284-285. IEEE, (2022)