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Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints.

, , , , , and . J. Electron. Test., 28 (4): 511-521 (2012)

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Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors., , , and . DSD, page 646-650. IEEE, (2020)Fast identification of true critical paths in sequential circuits., , , , and . Microelectron. Reliab., (2018)Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation., , , , , , and . EvoApplications, volume 8602 of Lecture Notes in Computer Science, page 425-436. Springer, (2014)BASTION: Board and SoC test instrumentation for ageing and no failure found., , , , , , , , and . DATE, page 115-120. IEEE, (2017)PASCAL: Timing SCA Resistant Design and Verification Flow., , , and . IOLTS, page 239-242. IEEE, (2019)Mixed hierarchical-functional fault models for targeting sequential cores., , , and . J. Syst. Archit., 54 (3-4): 465-477 (2008)Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors., , , , and . CoRR, (2021)A Novel Fault-Tolerant Logic Style with Self-Checking Capability., , , and . CoRR, (2023)On BTI Aging Rejuvenation in Memory Address Decoders., , , , , and . LATS, page 1-6. IEEE, (2022)Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules., , , and . DSD, page 557-561. IEEE, (2021)