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Disambiguation of "Devlin, Benjamin Stefan"

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Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA.

, , and . ISLPED, page 3-8. IEEE/ACM, (2011)

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Sam Devlin

Marie Devlin

Julia Devlin

Julia Mahnke-Devlin

Lorettann Devlin-Gascard

 

Other publications of authors with the same name

A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS., , and . ASP-DAC, page 75-76. IEEE, (2011)Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments., , and . IEICE Trans. Electron., 96-C (4): 518-527 (2013)A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1319-1328 (2010)Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes., , and . ASYNC, page 150-157. IEEE Computer Society, (2012)Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging., , , and . DFT, page 3. IEEE Computer Society, (2010)Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling., , and . IEICE Trans. Electron., 95-C (4): 546-554 (2012)Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system., , and . ICECS, page 53-56. IEEE, (2011)647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA., , , , and . ESSCIRC, page 156-159. IEEE, (2009)A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation., , and . IEEE J. Solid State Circuits, 46 (11): 2500-2513 (2011)Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA., , and . ISLPED, page 3-8. IEEE/ACM, (2011)