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Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies., , , , , , , and . IOLTS, page 129-134. IEEE, (2019)Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique., , , , and . CARLA, volume 697 of Communications in Computer and Information Science, page 131-145. (2016)MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1663-1673 (2022)Can We Trust Undervolting in FPGA-Based Deep Learning Designs at Harsh Conditions?, , , , and . IEEE Micro, 42 (3): 57-65 (2022)On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation., , and . SBAC-PAD, page 322-329. IEEE, (2018)Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories., , and . MICRO, page 724-736. IEEE Computer Society, (2018)Mth: Codesigned Hardware/Software Support for Fine Grain Threads., , and . IEEE Comput. Archit. Lett., 16 (1): 64-67 (2017)System-level power estimation tool for embedded processor based platforms., , , , , and . RAPIDO, page 5:1-5:8. ACM, (2014)Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins., , , , , , , and . CoRR, (2020)An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration., , , , , , , , and . DSN, page 138-149. IEEE, (2020)