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Disambiguation of "Yasuda, Takeo"

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Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).

, , , , , , , , , , , , , , , , , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Takeo Ohnishi

Yoshichiro Yasuda

Kiyotaka Yasuda

Takeo OÌ sawa

Kaori Sohar-Yasuda

 

Other publications of authors with the same name

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited)., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)High-speed wide-locking range VCO with frequency calibration.. ISCAS, page 45-48. IEEE, (2000)A low power CMOS circuit with Variable Souce Scheme (VSCMOS)., and . ASP-DAC, page 404-407. ACM, (2003)Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited)., , , , , , , , , and 13 other author(s). ISCAS, page 1-5. IEEE, (2023)On-chip temperature sensor with high tolerance for process and temperature variation.. ISCAS (2), page 1024-1027. IEEE, (2005)A dynamically phase adjusting PLL with a variable delay., , and . ASP-DAC, page 275-280. ACM, (2001)Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers., , , , , , , , , and 6 other author(s). ISCAS, page 3319-3323. IEEE, (2022)An On-Chip Power-on Reset Circuit for Low Voltage Technology., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (2): 366-372 (2002)An analog-AI chip for energy-efficient speech recognition and transcription., , , , , , , , , and 14 other author(s). Nat., 620 (7975): 768-775 (2023)