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Disambiguation of "Asai, Tetsuya"

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Design and evaluation of single-electron associative memory circuit.

, , and . Int. J. Parallel Emergent Distributed Syst., 32 (3): 259-270 (2017)

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Kwaichiro Asai

Tetsuya Takahashi

Yusuke Asai

Tetsuya Mizutani

Tetsuya Kawata

 

Other publications of authors with the same name

Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers., , , and . ICECS, page 140-143. IEEE, (2009)Silicon neuron design based on phase reduction analysis., , and . SCIS&ISIS, page 1059-1062. IEEE, (2012)Sensorless Force Control for Injection Molding Machine Using Reaction Torque Observer Considering Torsion Phenomenon., , , , , , and . IEEE Trans. Ind. Electron., 56 (8): 2955-2960 (2009)On Digital LSI Circuits Exploiting Collision-Based Fusion Gates., , , and . Int. J. Unconv. Comput., 4 (1): 45-59 (2008)Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator., , and . Int. J. Unconv. Comput., 7 (1-2): 53-63 (2011)Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits., , and . ICONIP (1), volume 6443 of Lecture Notes in Computer Science, page 188-195. Springer, (2010)Towards reaction-diffusion computing devices based on minority-carrier transport in semiconductors, , and . Chaos, Solitons & Fractals, 20 (4): 863--876 (May 2004)A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology., , , and . SMC, page 6. IEEE, (2002)Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation., , , , , , , , , and 1 other author(s). ICECS, page 169-172. IEEE, (2013)A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs., , , and . IEEE J. Solid State Circuits, 44 (7): 2047-2054 (2009)