Author of the publication

Stable high-order delta-sigma digital-to-analog converters.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 200-205 (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter., , , , , and . Integr., 42 (1): 24-33 (2009)Design of a switched opamp-based bandpass filter in a 0.35 μm CMOS technology., , , , , , and . ICECS, page 29-32. IEEE, (2002)Stable high-order delta-sigma digital-to-analog converters., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 200-205 (2004)Nonlinearity correction for multibit ΔΣ DACs., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (6): 1033-1041 (2005)Stable high-order delta-sigma DACS., , and . ISCAS (1), page 985-988. IEEE, (2003)Parallel Continuous-Time DeltaSigma ADC for OFDM UWB Receivers., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (7): 1478-1487 (2009)Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator., , , , , and . Microelectron. J., 42 (1): 148-157 (2011)Design of a CMOS fully differential switched-opamp for SC circuits at very low power supply voltages., , , , , , and . ICECS, page 1545-1548. IEEE, (2001)A 1.2 V, 130 nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers., , , , , and . Microelectron. J., 43 (4): 288-297 (2012)Effect of Finite amplifier Bandwidth and excess Loop Delay in a Parallel CT δς ADC for OFDM UWB receivers., , , , , and . J. Circuits Syst. Comput., (2013)